In microelectronics processing, transistors and other devices are formed on a substrate surface. The transistors and other devices are then interconnected with each other and external circuitry by multiple layers of metal lines and through vias which are formed over the transistors and other devices. Typically, the transistors and other devices are first contacted by metallic vias. Then, a number of alternating layers of metal lines (e.g., copper lines) and conductive through vias are formed to provide the interconnect structure. Two important factors in the performance of the interconnect structure are the resistance (R) of the conductive lines and vias and the capacitance (C) of the dielectric materials that separate the conductive lines and vias. The dielectric materials that separate the lines and vias are, in some cases, low dielectric constant (“low-k”) materials.
Low-k materials are used because they reduce the capacitance between adjacent metal lines and thereby improve the performance of the overall microelectronic device, for example by reducing RC delay. As transistors and the interconnect structures continue to become smaller and more advanced, it is desirable to continue to reduce the dielectric constant of the materials used. The lower limit for a dielectric constant is k=1, which is the dielectric constant of a vacuum. In order to approach this limit, methods and structures incorporating air gaps (air having a k value close to 1) into the interconnect structure have been proposed. Incorporating air gaps into the interconnect structure of a microelectronic device has numerous difficulties. In some processes, the metal lines may oxidize, which increases their electrical resistance and the likelihood of device failure.